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Senior FPGA Debug & Verification Architect
Job in
San Jose, Santa Clara County, California, 95199, USA
Listed on 2026-06-05
Listing for:
Altera
Full Time
position Listed on 2026-06-05
Job specializations:
-
Engineering
Test Engineer, Systems Engineer
Job Description & How to Apply Below
Altera is seeking a Senior Debug Verification Engineer in San Jose, California to oversee design verification tasks including creating test cases and employing UVM methodology.
The ideal candidate will have over 8 years of experience in ASIC designs, System Verilog, and UVM verification methodologies. Key responsibilities include pre-silicon system verification, creating test cases, and coordinating with cross-functional teams. The salary range for this position is $149,100 - $215,000 per year.
#J-18808-LjbffrPosition Requirements
10+ Years
work experience
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