ASIC Engineering Technical Leader; Onsite

The application window is expected to close on: 06/26/2026.

Job posting may be removed earlier if the position is filled or if a sufficient number of applications are received.

As a Failure Analysis Engineer, you will be part of the Quality and Reliability group, performing failure analysis of ASIC products. Should have a passion for problem solving and a strong technical background in semiconductor failure analysis techniques and root cause analysis.

You have the required experience with a variety of semiconductor failure analysis techniques and test equipment along with the ability to interpret results and provide clear guidance on causes of failure.

Your role will require high level of collaboration and interaction with Product Test Engineering, Design Engineering, Quality Engineering, Assembly Engineering and Foundry Engineering teams.

Responsibilities include:

• Conduct root cause failure analysis of silicon product reliability test and field failures and propose corrective actions.
• Develop and implement standard processes for failure analysis using all types of FA techniques and equipment.
• Coordinate all the logistics and instructions to direct the failure analysis process and carry out FA function in a systematic way.
• Document and report failure analysis results to management.
• Function as a technical resource for failure analysis questions.
• Develop and maintain relationships with FA service and equipment vendors.

• Bachelor's degree in Electrical/Electronics Engineering or related required. Masters preferred.
• 10+ years of experience in semiconductor failure analysis field.
• Proven track record writing and executing FA plans and interpret results from FA techniques such as cross section, X-ray, CSAM, TDR, FIB, SEM, and TEM, IR/EMMI/OBIRCH.
• Validated ability to specify hardware and implement set up for dynamic FA using SIL (Solid Immersion Lens) and LSM (Laser Scanning Microscopy).
• Working knowledge of fault isolation techniques using ATE, Scan/ATPG, MBIST to identify, isolate and characterize device-level faults.

• Semiconductor technology and process knowledge (Fab, Assembly, and Advanced Packaging).
• Good understanding of transistor function/basic electronics, semiconductor device physics and behavior under various operating conditions.
• Working knowledge to understand ATE test data to categorize the failures.
• Knowledge of JEDEC IC Qualification tests and requirements is beneficial.
• Proven experience driving physical failure analysis with suppliers.
• Interface with product, test, and design engineering groups to identify and characterize faults on emerging technologies, while providing fault isolation, identification, and characterization for yield/reliability failures.
• Enjoy hands‑on work and working in a lab environment.
• Good customer and vendor management skills.
• Ability to work well in multi‑functional teams in a fast‑paced, collaborative team environment.

The starting salary range posted for this position is $ to $ and reflects the projected salary range for new hires in this position in U.S. and/or Canada locations, not including incentive compensation, equity, or benefits.

Individual pay is determined by the candidate's hiring location, market conditions, job-related skillset, experience, qualifications, education, certifications, and/or training. The full salary range for certain locations is listed below. For locations not listed below, the recruiter can share more details about compensation for the role in your location during the hiring process.

U.S. employees are offered benefits, subject to Cisco’s plan eligibility rules, which include medical, dental and vision insurance, a 401(k) plan with a Cisco matching contribution, paid parental leave, short and long‑term disability coverage, and basic life insurance. Employees may be eligible to receive grants of Cisco restricted stock units, which vest following continued employment with Cisco for defined periods of time.

• 10 paid holidays per full calendar year, plus 1 floating holiday for…