RFIC Layout Manager

Responsibilities

We are seeking an experienced and accomplished Senior Manager – RFIC Layout to lead and drive layout development for complex RF/Analog ICs. This role requires strong technical expertise, proven leadership capabilities, and the ability to manage large teams while owning end-to-end layout delivery across product lines. The ideal candidate will play a critical role in mentoring teams, enabling advanced technology adoption, and ensuring high-quality execution in a cross‑functional environment.

• Lead and manage RF/Analog layout teams, ensuring high-quality and timely delivery of design projects
• Own end-to-end layout development across product lines with strong accountability
• Mentor, train, and scale teams including freshers and contractors
• Drive floor‑planning for complex RF/Analog chips and IPs considering noise and isolation constraints
• Provide technical leadership in RF signal path and high‑speed design implementations
• Collaborate with cross‑functional teams including ASIC, PnR, CAD, and Packaging
• Ensure compliance with Analog IP deliverables, QC processes, and release flows
• Enable team readiness for advanced technology nodes and evolving design challenges

• Tech/B.E. with 20+ years of experience in RF/Analog layout.
• Experience in managing/mentoring large teams consisting of 20+ members
• Strong communication skills with proven track record of owning layout development from product lines.
• Strong Technical mentorship skills, Ability to hire/train teams train including freshers/contractors
• Should have floor‑planning experience for Complex RF/Analog chips & IPs which may need magnetic coupling isolation constraints and noise isolation constraints.
• Experience in handling chipsets/top-levels in Wireless/Wi‑Fi transceivers and proficiency with RF signal path building blocks such as LNA, mixers, RFPLLs, PA, Multi‑GHz ADCs and DACs would be added advantage.
• Experience with High speed Serdes Designs (PAM4, PCIe, etc.) and hands on experience in building blocks of Serdes (CTLE, ADCs, DACS, PLL, High speed Clock distribution, etc.).
• Good exposure to Fin‑FET technology challenges (5nm, 3nm) and should be able to ramp up the team on new technology nodes.
• Should have a good overview of the Deliverables/QC of an Analog IP into SoC context and release flows.
• Should have good cross‑functional knowledge/deliverables with other teams such as ASIC, PnR, CAD and Packaging teams.
• Knowledge in ESD/IO design will be added advantage