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Design Verification Engineering Lead - Silicon One
Job in
San Jose, Santa Clara County, California, 95115, USA
Listed on 2026-06-11
Listing for:
Cisco
Full Time
position Listed on 2026-06-11
Job specializations:
-
Engineering
Systems Engineer, Hardware Engineer, Software Engineer -
IT/Tech
Systems Engineer, Hardware Engineer
Job Description & How to Apply Below
** Job posting may be removed earlier if the position is filled or if a sufficient number of applications are received** .
** Meet the Team:*
* Come join us and take part in shaping Cisco's revolutionary solutions for data centers by designing some of the most complex chips being developed in the industry with the opportunity to get full exposure to all aspects of the systems and applications we build (Silicon, Hardware, Software, telemetry, security, etc). Our group offers a unique combination of a startup culture with the benefits of working for the leading networking company in the world!
** What You'll Do:*
* As an ASIC Design Verification Engineer, you will play a critical role in developing Cisco's revolutionary data center solutions. You'll architect and develop DV infrastructure, create and execute comprehensive test plans, and ensure robust verification and coverage for complex chips. Your collaboration with designers, architects, and software teams will help guarantee seamless integration and optimal performance of Cisco's hardware platforms.
** You will:*
* + Architect block, cluster and top level DV environment infrastructure
+ Create DV infrastructure from scratch for block, cluster and top-level environments
+ Maintaining existing DV environments and enhancing them
+ Ensuring complete verification coverage through implementation and review of code and functional coverage
+ Working closely with ASIC designers
+ Supporting tests done with emulation
+ Work closely with software teams and debug issues found during firmware development
+ Responsible for ASIC bring up
*
* Minimum Qualifications:
*
* + Typically:
Bachelors + 12 years of related experience, or Masters + 8 years of related experience, or PhD + 5 years of related experience
+ Prior experience with Verilog, System Verilog, and UVM within the last 2-3 years.
+ Prior experience with scripting languages (i.e Perl or Python)
+ Prior experience with ASIC design and verification processes, debugging, methodology, and tools.
+ Prior experience in verifying blocks/clusters or full chip level for ASIC.
*
* Preferred Qualifications:
*
* +
Experience with Linux, C/C++, and/or Python/Perl.
+
Experience with Veloce/Palladium/Zebu/HAPS is a plus
+ Post-silicon lab bring-up experience.
+ Strong domain experience on one or more protocols - PCIe, Ethernet, RDMA, TCP, Fiber Channel (FC)
+
Experience with Formal verification (iev/vc formal/Jasper Gold)
+
Experience with AI agents (i.e Cursor, Codex, CoPilot, etc...)
+ Lead verification for a complete SOC or ASIC is a plus
+
Experience with Forwarding logic/Parsers/P4 is a plus
** Why Cisco?*
* At Cisco, we're revolutionizing how data and infrastructure connect and protect organizations in the AI era - and beyond. We've been innovating fearlessly for 40 years to create solutions that power how humans and technology work together across the physical and digital worlds. These solutions provide customers with unparalleled security, visibility, and insights across the entire digital footprint.
Fueled by the depth and breadth of our technology, we experiment and create meaningful solutions. Add to that our worldwide network of doers and experts, and you'll see that the opportunities to grow and build are limitless. We work as a team, collaborating with empathy to make really big things happen on a global scale. Because our solutions are everywhere, our impact is everywhere.
We are Cisco, and our power starts with you.
** Message to applicants applying to work in the U.S. and/or Canada:*
* The starting salary range posted for this position is $ to $ and reflects the projected salary range for new hires in this position in U.S. and/or Canada locations, not including incentive compensation*, equity, or benefits.
Individual pay is determined by the candidate's hiring location, market conditions, job-related skillset, experience, qualifications, education, certifications, and/or training. The full salary range for certain locations is listed below. For locations not listed below, the recruiter can share more details about compensation for the role in your location during the…
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