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Design Engineer - ASIC​/RTL

Job in San Jose, Santa Clara County, California, 95199, USA
Listing for: Infobahn Softworld Inc
Full Time position
Listed on 2026-06-12
Job specializations:
  • Engineering
    Systems Engineer, Hardware Engineer, Electronics Engineer
Salary/Wage Range or Industry Benchmark: 100000 - 125000 USD Yearly USD 100000.00 125000.00 YEAR
Job Description & How to Apply Below

The work will expose the designer to a number of IP including ARM cores, Ethernet, DDR, DMA, PCIE, SATA and AMD internal IPs. Successful candidates will be responsible for leading, and participating in, the design of leading edge SoCs in advanced digital CMOS processes.

Our RTL Design Engineers are expected to contribute in all aspects of SoC design including:

  • Chip definition
  • Architecture development and modeling
  • Development of micro-architectural specifications
  • Conversion of micro-architectural specifications to logic implementation
  • Verification
  • Emulation
  • Debug
  • Synthesis and timing closure
  • Interfacing with physical execution, software, and silicon bring-up teams
EXPERIENCE AND

EDUCATION:
  • Strong knowledge and hands‑on experience from industry ASIC design flow, including RTL coding, debugging/verification, and supporting synthesis and timing closure
  • Working knowledge of ARM cores and other I/O standard interfaces
  • Strong communication and documentation skills
  • Good organizational, time management and multitasking skills
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