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SoC​/ASIC Design Engineer — RTL & FPGA Config

Job in San Jose, Santa Clara County, California, 95199, USA
Listing for: AMD
Full Time position
Listed on 2026-06-12
Job specializations:
  • Engineering
    Systems Engineer, Hardware Engineer, Electronics Engineer
Salary/Wage Range or Industry Benchmark: 100000 - 125000 USD Yearly USD 100000.00 125000.00 YEAR
Job Description & How to Apply Below
A leading technology company located in San Jose is seeking motivated candidates for a role involving complex microarchitectural design and FPGA configuration. The ideal applicant has a Bachelor’s or Master’s in Electrical or Computer Engineering, and a background in ASIC design with skills in Verilog, System Verilog, and collaboration across multiple teams. This role is pivotal for driving next-generation configuration solutions and requires strong communication and analytical skills.
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