Design Verification Engineering Lead - Silicon One Job San Jose area,California USA,Engineering

The application window is expected to close on 08/25/2026. Job posting may be removed earlier if the position is filled or if a sufficient number of applications are received.

Meet the Team:

Come join us and take part in shaping Cisco’s revolutionary solutions for data centers by designing some of the most complex chips being developed in the industry. Our team offers a unique combination of startup culture with the benefits of working for the leading networking company in the world.

What You’ll Do:

As an ASIC Design Verification Engineer, you will architect and develop DV infrastructure, create and execute comprehensive test plans, and ensure robust verification and coverage for complex chips. You will collaborate with designers, architects, and software teams to guarantee seamless integration and optimal performance of Cisco’s hardware platforms.

You will:

Architect block, cluster, and top‑level DV environment infrastructure
Create DV infrastructure from scratch for block, cluster and top‑level environments
Maintain and enhance existing DV environments
Ensure complete verification coverage through implementation and review of code and functional coverage
Work closely with ASIC designers
Support tests performed with emulation
Collaborate with software teams and debug issues found during firmware development
Be responsible for ASIC bring‑up

Minimum Qualifications:

Bachelor’s degree + 12 years of related experience, or Master’s degree + 8 years of related experience, or PhD + 5 years of related experience
Prior experience with Verilog, System Verilog, and UVM within the last 2–3 years
Experience with scripting languages (Perl or Python)
Experience with ASIC design and verification processes, debugging, methodology, and tools
Experience verifying blocks, clusters, or full chip level for ASIC

Preferred Qualifications:

Experience with Linux, C/C++, and/or Python/Perl
Experience with Veloce/Palladium/Zebu/HAPS
Post‑silicon lab bring‑up experience
Strong domain experience on protocols such as PCIe, Ethernet, RDMA, TCP, or Fiber Channel (FC)
Experience with formal verification (e.g., System Verilog Assertions, formal verification tools)
Experience with AI agents (e.g., Codex, CoPilot) beneficial
Lead verification for a complete SOC or ASIC a plus
Experience with Forwarding logic, Parsers, or P4 a plus

Compensation and Benefits:

Starting salary range: $ to $ for U.S. and/or Canada locations. Employees receive a comprehensive benefits package including medical, dental, vision, a 401(k) plan with matching, paid parental leave, short‑ and long‑term disability coverage, and basic life insurance. Additional benefits such as paid holidays, vacation time, and the possibility of equity awards are also available.

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