Sr Memory Subsystem Verification Engineer

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Together, we advance your career.

Join AMD’s Adaptive and Embedded Computing Group (AECG) and help shape the future of high‑performance computing. We are seeking an experienced Silicon Design Verification Engineer to play a pivotal role in delivering next‑generation silicon by driving pre‑silicon verification for advanced Network‑on‑Chip (NoC) architectures and cutting‑edge DRAM memory controller IPs (LPDDR6, HBM4).

In this role, you won’t just verify designs—you’ll influence architecture, elevate quality, and help ensure first‑pass silicon success on some of the industry’s most advanced technologies. You’ll work across IP and SoC levels, leveraging state‑of‑the‑art simulation and formal verification techniques in a highly collaborative, innovation‑driven environment.

You are a proven verification expert with a passion for solving complex challenges and delivering high‑quality silicon. You bring a strong track record of executing verification strategies for IP and/or SoC designs and thrive in fast‑paced, technically demanding environments.

You’re not just a contributor—you’re an influencer. With strong communication and leadership skills, you collaborate effectively across design, architecture, and software teams, helping drive decisions that improve product quality and execution. You also enjoy mentoring others and elevating the team around you.

• Drive verification of advanced NoC architectures and next‑generation DRAM memory controllers (LPDDR6, DDR5, HBM4), ensuring best‑in‑class quality and performance
• Architect, develop, and optimize simulation and formal‑based verification environments at both IP and SoC levels
• Own the full verification lifecycle: planning, execution, tracking, closure, and delivery
• Create and execute robust verification plans, including sophisticated test benches and coverage‑driven test strategies
• Partner cross‑functionally with design, architecture, and software teams to define and implement scalable verification methodologies
• Apply advanced techniques including UVM, assertion‑based verification, and formal methods
• Mentor and guide junior engineers, fostering a culture of technical excellence and continuous innovation

• Demonstrated success driving verification strategy and execution for NoC and/or memory controller IPs
• Strong expertise in System Verilog and UVM, with hands‑on experience in simulation tools such as Synopsys VCS or Cadence Xcelium
• Deep understanding of modern verification methodologies, including assertion‑based and coverage‑driven verification
• Experience shaping verification architecture, tools, and infrastructure for complex, high‑performance silicon designs is highly valued
• Familiarity with regression and verification management tools, including database‑driven workflows
• Exposure to formal verification tools such as VC Formal, Jasper Gold, or Questa Formal is a plus
• Experience with gate‑level simulation, power‑aware verification, or silicon debug (tester/board level) is a plus

• BS, MS, or PhD in Electrical Engineering, Computer Engineering, Computer Science, or related field

This role is not eligible for visa sponsorship.

Benefits offered are described: AMD benefits at a glance.

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee‑based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third‑party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.

We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s Responsible AI Policy is available here.

This posting is for an existing vacancy.