SI​/PI Intern

About Etched

Etched is building the world’s first AI inference system purpose-built for transformers - delivering over 10x higher performance and dramatically lower cost and latency than a B200. With Etched ASICs, you can build products that would be impossible with GPUs, like real-time video generation models and extremely deep & parallel chain-of-thought reasoning agents. Backed by hundreds of millions from top-tier investors and staffed by leading engineers, Etched is redefining the infrastructure layer for the fastest growing industry in history.

As a Signal Integrity / Power Integrity Intern, you will help design and validate the next generation of high-performance AI systems. You will work closely with package, PCB, ASIC, and system engineers to analyze high-speed interfaces, extract channel models, and improve signal quality across our accelerator platforms.

This role provides hands‑on experience with industry-leading tools and real‑world challenges involving PCIe, Ethernet, high-speed Ser Des channels, advanced packaging, and multi‑board systems.

• Signal Integrity Analysis
• Perform channel analysis for high-speed interfaces including PCIe, Ethernet, and other Ser Des links. Extract and validate S-parameter models from package and PCB layouts. Analyze insertion loss, return loss, impedance discontinuities, and crosstalk. Generate channel compliance reports and support design reviews. Modeling & Simulation.
• Build and validate 3D electromagnetic models using Ansys HFSS. Develop board and package channel models from ECAD design databases. Correlate simulation results with measurements and lab data. Support mixed package‑board channel simulations and optimization. Design collaboration.
• Partner with PCB layout, package, hardware, and ASIC teams to improve signal integrity. Identify root causes of channel degradation and propose design improvements. Contribute to SI design guidelines and best practices. Representative projects.
• Extract S-parameter models from package and board designs for PCIe channels. Build HFSS models of high-speed breakout regions and BGA transitions. Perform channel compliance analysis for Ethernet links. Investigate impedance discontinuities and optimize via structures. Develop automated workflows for SI simulation and report generation. You may be a good fit if you have.
• Progress toward a BS, MS, or PhD in Electrical Engineering, Computer Engineering, or a related field. Coursework or project experience in signal integrity, electromagnetics, RF, microwave engineering, or high-speed digital design. Familiarity with transmission line theory and S-parameters. Understanding of PCB stackups, routing, and high-speed design fundamentals. Strong analytical and debugging skills. Excellent communication and collaboration skills. Strong candidates may also have.
• Experience with Ansys HFSS, SIwave, ADS, CST, or similar simulation tools.
  
  Experience with PCIe, Ethernet, DDR, or other high-speed interfaces. Familiarity with Allegro, APD, ODB++, IPC
  2581, or other ECAD databases. Experience processing Touchstone files and channel metrics. Python scripting for simulation automation and data analysis. Experience with laboratory measurements using VNAs, oscilloscopes, or TDR equipment. We encourage you to apply even if you do not believe you meet every qualification.

• 12-week paid internship
• Generous housing support for those relocating
• Daily lunch and dinner in our office
• Based at our office in San Jose, CA
• Direct mentorship from industry leaders and world-class engineers
• Opportunity to work on one of the most important problems of our time

For any questions, contact

Etched believes in the Bitter Lesson. We think most of the progress in the AI field has come from using more FLOPs to train and run models, and the best way to get more FLOPs is to build model-specific hardware. Larger and larger training runs encourage companies to consolidate around fewer model architectures, which creates a market for single-model ASICs.

We are a fully in-person team in West San Jose, and greatly value engineering skills. We do not have boundaries between engineering and research, and we expect all of our technical staff to contribute to both as needed.