Speed SerDes Principal Engineer

Overview

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

The Principal Analog IC Designer is responsible for the design and development of analog/mixed signal IC circuit blocks from initial concept/specification through final verification of conformance to customer specifications.

Candidate’s background should include a minimum of 7 years of experience in CMOS Ser Des or high-speed I/O IC design and development

• Design and develop analog/mixed signal IC circuit blocks from concept/specification to verification against customer specifications.
• Proficient design experience in Ser Des blocks including Driver, Receiver, Serializer, Deserializer, Phase Interpolator, Low jitter PLL, High Speed Clock Distribution, ADC and DAC, Bias and Bandgap, and Voltage Regulators.
• Proficient use of CAD tools for circuit simulation, layout, and physical verification.

• Minimum 7 years of experience in CMOS Ser Des or high-speed I/O IC design and development.
• Working knowledge of a set of common Ser Des standards and their electrical requirements is a plus.
• Thorough understanding of jitter and signal equalization techniques.
• Excellent problem solving skills, analog aptitude, good communication skills, and ability to work cooperatively in a team environment.
• MS or PhD in Electrical Engineering.
• Cadence tool experience, lab test experience, and design experience at >10
  
  Gbps and in