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Senior DFT Design Engineer FPGA​/SoC Innovation

Job in San Jose, Santa Clara County, California, 95199, USA
Listing for: Altera
Full Time position
Listed on 2026-06-15
Job specializations:
  • Engineering
    Engineering Design & Technologists, Electronics Engineer, Test Engineer, Systems Engineer
Salary/Wage Range or Industry Benchmark: 60000 - 80000 USD Yearly USD 60000.00 80000.00 YEAR
Job Description & How to Apply Below
Position: Senior DFT Design Engineer for FPGA/SoC Innovation

Altera is seeking a DFT Design Engineer in San Jose, California, to define and implement DFT architectures for complex IC designs. This role involves working on advanced technologies, collaborating with design and test teams to ensure manufacturability and efficiency.

The ideal candidate has substantial experience in DFT at both RTL and gate levels, EDA tools for test logic insertion and validation, and proficiency in scripting. A Bachelor's or Master's degree in Engineering is essential.

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Position Requirements
10+ Years work experience
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