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Dir, CAD Eng • R&D

Job in San Jose, Santa Clara County, California, 95199, USA
Listing for: Lattice
Full Time position
Listed on 2026-06-16
Job specializations:
  • Engineering
    Systems Engineer
Salary/Wage Range or Industry Benchmark: 160000 - 200000 USD Yearly USD 160000.00 200000.00 YEAR
Job Description & How to Apply Below

Responsibilities & Skills

Description:
Director – CAD Design Engineering & EDA Infrastructure

Role Overview

The Director of EDA Design Methodology & Infrastructure will lead the development, deployment, and optimization of design automation flows, tools, and infrastructure across the organization. This role ensures that engineering teams have cutting‑edge, scalable, and efficient methodologies to deliver complex semiconductor designs on time and with high quality.

Key Responsibilities
  • EDA Strategy
    :
    Define and drive the long‑term vision for EDA methodologies, flows, and infrastructure to support advanced semiconductor design.
  • Methodology Development
    :
    Architect and implement design flows for RTL-to-GDSII, verification, physical design, timing closure, and sign‑off.
  • Infrastructure Management
    :
    Oversee compute farms, license servers, cloud integration, and tool deployment to ensure scalability and efficiency.
  • GenAI Strategy for the EDA Design and Methodology
  • Cross-functional Collaboration
    :
    Partner with design, verification, CAD, and IT teams to align methodologies with project needs.
  • Tool Evaluation
    :
    Evaluate, benchmark, and deploy EDA tools from major vendors; negotiate with suppliers to optimize cost and performance.
  • Innovation Leadership
    :
    Introduce automation, AI/ML-driven flows, and cloud‑native solutions to accelerate design productivity.
  • Team Leadership
    :
    Build and mentor a high‑performing team of CAD/EDA engineers; foster a culture of technical excellence and innovation.
  • Process Standardization
    :
    Establish best practices, documentation, and training programs for design teams worldwide.
  • Risk Management
    :
    Identify and mitigate risks in tool flows, infrastructure, and project schedules.

Qualifications

  • Education
    :
    Master’s in electrical engineering, Computer Engineering, or related field.
  • Experience
    : 15+ years in semiconductor design, with at least 7 years in EDA methodology leadership.
  • Technical Expertise
    :
    Deep knowledge of RTL design, verification, synthesis, place & route, timing analysis, and sign‑off flows.
  • Infrastructure Knowledge
    :
    Strong background in compute infrastructure, cloud‑based design environments, and license management.
  • Leadership Skills
    :
    Proven ability to lead global teams, manage vendor relationships, and drive organizational change.
  • Soft Skills
    :
    Excellent communication, negotiation, and strategic planning abilities.
Impact

This role is pivotal in enabling the company to design next‑generation chips efficiently and competitively. By leading EDA methodology and infrastructure, the director ensures that engineering teams can innovate faster, reduce time‑to‑market, and maintain design quality at scale.

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