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Senior Principal IC Design Verification Application Engineer

Job in San Jose, Santa Clara County, California, 95199, USA
Listing for: Cadence Design Systems
Full Time position
Listed on 2026-06-17
Job specializations:
  • Engineering
    Hardware Engineer, Systems Engineer, Test Engineer, Electronics Engineer
Salary/Wage Range or Industry Benchmark: 143500 - 266500 USD Yearly USD 143500.00 266500.00 YEAR
Job Description & How to Apply Below

Position Overview

Cadence seeks an energetic and innovative Application Engineer for our Verification Field Applications Engineering (AE) team. The role works closely with industry leaders, supporting pre‑ and post‑sales technical support and driving customer success by developing customer‑specific verification requirements, advanced verification component development, methodology support, and maintaining Cadence’s verification tools and services.

Key Responsibilities
  • Establish technical credibility and rapport with customers and act as the go‑to expert for technical inquiries and support.
  • Collaborate with R&D to provide in‑depth technical assistance for advanced verification flows and AI/ML applications to secure design wins.
  • Champion the customer’s needs and work with R&D and marketing to develop competitive and creative technical solutions.
  • Understand the competitive landscape and continuously work to differentiate Cadence’s solutions.
  • Write technical product literature such as application notes and technical articles.
  • Review new product proposals and device specifications.
  • Assume technical leadership roles in small teams as needed.
Qualifications

Minimum: BS, MS, or PhD in Computer Science/Engineering, Electrical Engineering, or related field; 7+ years experience with System Verilog, VHDL, Verilog; verification skills such as UVM testbench architecture, development, and debug; strong RTL and Testbench debug skills; scripting (Perl, Python or Tcl); strong software, HDL design and verification skills; ability to quickly analyze verification environments and design complexity; strong verbal and written communication skills;

strong teamwork skills; ability to interact effectively with both external customers and R&D teams.

Preferred: Experience with C/C++/SystemC; deploying VIPs in test benches; knowledge of protocols like JTAG, UART, PCIe, AMBA, DDR; understanding of design fundamentals such as architecture, micro‑architecture, HDLs, synthesis, and timing; digital design experience.

Compensation

Annual salary range for California is $143,500 to $266,500. Candidates may also be eligible for incentive compensation (bonus, equity). Compensation may vary based on qualifications, skill level, competencies, and work location.

Benefits

Paid vacation and paid holidays, 401(k) plan with employer match, employee stock purchase plan, medical, dental, and vision plans.

Equal Employment Opportunity

Cadence is committed to equal employment opportunity throughout all levels of the organization. Cadence is proud to be an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to race, color, sex, age, national origin, religion, sexual orientation, gender identity, status as a veteran, basis of disability, or any other protected class.

Legal Statements

Cadence participates in the E-Verify program in certain U.S. locations as required by law.

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Position Requirements
10+ Years work experience
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