Senior FPGA Compiler; Router Engineer

Position Overview

Altera is seeking a Senior FPGA Compiler Engineer (Routing) to join our team. This role focuses on the development and optimization of FPGA routing algorithms within the compiler toolchain, directly impacting performance, power, and usability of next-generation FPGA devices.

• Routing Algorithm Development:
  Design, implement, and optimize FPGA routing algorithms to improve performance, routability, and timing closure.
• Compiler Enhancement:
  Contribute to the FPGA compiler flow, including placement, routing, and timing‑driven optimization.
• Performance Optimization:
  Analyze and improve runtime, memory efficiency, and scalability of routing algorithms for large designs.
• Cross‑Functional
  
  Collaboration:
  
  Work closely with architecture, synthesis, timing (STA), and hardware teams to align routing strategies with device capabilities.
• Debug & Analysis:
  Investigate routing congestion, timing violations, and design bottlenecks; develop solutions to improve convergence.
• Toolchain Integration:
  Integrate routing features into existing compiler infrastructure and ensure robustness across diverse customer use cases.

• 9+ years of experience in FPGA/ASIC design tools, EDA, or related fields.
• Strong background in algorithms and data structures (graph algorithms, optimization techniques).
• Experience with FPGA or ASIC design flows (placement, routing, timing closure).
• Proficiency in C/C++ and software development best practices.
• Familiarity with routing algorithms (e.g., maze routing, negotiated congestion), timing‑driven design methodologies, and physical design concepts.
• Ability to analyze complex systems and develop scalable, high‑performance solutions.
• Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, Computer Science, or related field.
• Strong communication, teamwork, and interpersonal skills.

• Experience with commercial FPGA tool chains (Quartus, Vivado).
• Knowledge of FPGA architectures and interconnect fabrics.
• Familiarity with parallel/distributed computing for EDA workloads.
• Experience with scripting (Python, Tcl) for tooling and automation.
• Background in timing analysis or placement algorithms.

$187.0K – $270.7K USD. Incentive opportunities that reward employees based on individual and company performance.

• Job Type: Regular
• Shift: Shift 1 (United States of America)
• Primary
  
  Location:
  
  San Jose, California, United States

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.