SoC RTL Design Engineer Job San Jose area,California USA,Engineering

Specify and own the reset sequencing architecture. Own the secure boot and fuse micro architecture and design.
Coordinate with the subsystem leads on reference clock distribution, clock-domain crossing points at subsystem interfaces.
Collaborate with the firmware team to define the hardware/software interface: interrupt controller, timer, UART/JTAG debug port, and any DMA or mailbox channels
Own the clock-gating implementation strategy: coarse-grain vs. fine-grain gating, ICG cell selection, and sign-off methodology for dynamic power reduction.
Define the chip-level power-domain plan: which blocks share supplies, where level-shifters and isolation cells are required, and how power states map to the PCIe and UCIe link power management protocols.
Own the on-chip power management logic: power-state machine, supply sequencing, voltage regulator integration, and the firmware interface for runtime power control.
Drive power intent (UPF/CPF) authoring and sign-off, coordinating with physical design team on power-domain floorplan, always-on routing, and isolation verification.
Own the embedded management processor subsystem: processor integration, on-chip SRAM and ROM sizing, boot sequence, fuse and OTP interface, and the firmware execution environment.
Define the management register map: the address space through which firmware configures operating modes, reads telemetry, controls power states, and manages DFT operations.
Specify thermal monitoring integration: on-die temperature sensor placement, readout path to the management processor, and thermal throttling hooks.

Required Qualifications

BS/MS in Electrical Engineering, Computer Engineering, or equivalent. 8+ years of digital IC design, with at least 3 years owning chip infrastructure — clocking, power management, reset or DFT — at block-lead or subsystem-owner level.
Familiarity with embedded microcontroller integration: memory maps, boot ROM, interrupt controllers, and firmware bring-up at the hardware level.
Experience with reset-domain architecture and reset synchronizer design in multi-power-domain chips.
Strong System Verilog skills for infrastructure RTL: clock-gating cells, power FSMs, scan-enable muxing, and BIST controllers.

Preferred Qualifications

Background integrating a RISC-V or ARM Cortex-M class processor as a management/configuration engine in a non-CPU chiplet.
Exposure to hardware security: secure boot, anti-tamper fuse programming, or related infrastructure.

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