ASIC​/RTL Design Engineer

Our client, an American multinational semiconductor company headquartered in Santa Clara, California, is seeking an ASIC/RTL Design Engineer to join their team.

Job Title: ASIC/RTL Design Engineer

Project Duration: 6+ months

Location: 2100 Logic Drive, San Jose, CA 95124, United States

The work will expose the designer to a number of IP including ARM cores, Ethernet, DDR, DMA, PCIE, SATA and AMD internal IP. Successful candidates will be responsible for leading, and participating in, the design of leading edge SoCs in advanced digital CMOS processes. Our RTL Design Engineers are expected to contribute in all aspects of SoC design including chip definition, architecture development and modeling, development of micro‑architectural specifications, conversion of micro‑architectural specifications to logic implementation, verification, emulation, debug, synthesis, and timing closure, and interfacing with physical execution, software, and silicon bring‑up teams.

SoC architecture; knowledge and hands‑on experience from industry ASIC design flow including RTL coding, debugging/verification, and supporting synthesis and timing closure. Working knowledge of ARM cores and other I/O standard interfaces. An ideal candidate would also exhibit strong communication and documentation skills, good organizational, time‑management and multitasking skills, strong initiative and discipline to follow through, and technical leadership.