FPGA Silicon Design Engineer

About Altera

Altera™ is the world’s largest pure‑play FPGA solutions provider with more than four decades of industry‑leading expertise. Our mission is to deliver programmable technologies that help customers differentiate, innovate, and scale across AI, cloud, networking, and edge markets. As an independent company, we move faster, invest deeper, and partner more closely to empower teams to drive breakthrough innovation and shape the future of the FPGA industry.

FPGA Silicon Design Engineer focused on RTL design. Responsible for developing high‑quality logic designs and RTL implementations for next‑generation FPGA products. Collaborate cross‑functionally with architecture, verification, and physical design teams to deliver robust, high‑performance silicon solutions. This position plays a critical role in enabling scalable, power‑efficient FPGA architectures used across a wide range of applications.

• Develop logic design, register transfer level (RTL) coding, and simulation for FPGA components including cell libraries, functional units, IP blocks, and subsystems.
• Participate in defining architecture and microarchitecture features of assigned design blocks.
• Create prototypes, simulate models, and define system requirements for new designs.
• Prepare and design logic diagrams and RTL code to implement system design and test specifications.
• Deliver software models to support device‑level bring‑up, including functionality, timing, and power characteristics.
• Apply RTL implementation techniques to meet power, performance, and area (PPA) goals in partnership with physical design teams.
• Review verification plans and ensure proper implementation to validate design features.
• Debug failing RTL tests, identify root causes, and implement corrective actions to ensure design correctness.

Bay Area, California: $149,100 – $215,925 USD. Actual salary may vary based on location, job‑related knowledge, skills, experience, and trainings. We also offer incentive opportunities that reward employees based on individual and company performance.

• Bachelor’s degree in Electrical Engineering, Computer Engineering, Computer Science, Physics, Math, or related field.
• 8+ years of industry experience in FPGA or ASIC design.
• 8+ years of experience in RTL design and coding using System Verilog and/or Verilog for complex digital systems.
• 8+ years of experience with programming/scripting languages such as Python for design automation, modeling, or verification support.
• 8+ years of experience in hardware design concepts including logic design, finite state machines, control units, processor subsystems, and network‑on‑chip (NoC) architectures.
• 8+ years of experience using industry‑standard front‑end design tools and flows, including synthesis, static timing analysis (STA), linting (e.g., Spy Glass), and power domain methodologies.
• 8+ years of experience collaborating with cross‑functional teams (verification, physical design) to achieve power, performance, and area (PPA) targets.

• Knowledge of Network‑on‑Chip (NoC) architectures and control processors.
• Experience contributing to silicon bring‑up or post‑silicon validation.
• Experience or knowledge in FPGA configuration controllers.

Job Type: Regular

Shift: Shift 1 (United States of America)
Primary

Location:

San Jose, California, United States

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.