RTL Design Data Center Chassis

Overview

Media Tek’s Data Center team is at the forefront of innovation, driving the development of cutting-edge technologies for the world s most advanced data centers. We are a dynamic group of system architects, packaging technology developers, and SoC design experts dedicated to creating high-performance, efficient, and reliable solutions. Our team collaborates to push the boundaries of technology, ensuring optimal performance, power efficiency, and scalability for data center applications.

The Data Center Chassis Lead will be responsible for architecting, adopting, and designing chip/chiplet chassis building blocks for data center silicon, including reviewing chassis building blocks, collaborating with the chassis domain lead to architect a version for data center, coordinating with the SoC/Chip/Chiplet design lead for integration requirements, execution plans, and implementation, and providing improvements based on analysis results along with thorough design verification and documentation.

• Review chassis building blocks and collaborate with the chassis domain lead to architect and tailor versions for data center silicon.
• Work with the SoC/Chip/Chiplet design lead to define integration requirements, execution plans, and implementation steps.
• Provide improvements based on analysis results and conduct thorough quality design verification and documentation.

• MS in Electrical Engineering, Computer Engineering, or a related field.
• 5+ years of experience in designing transistor-level digital circuits.
• 3+ years of hands-on experience in architecting and designing chassis for data center silicon.
• Strong knowledge of SoC/Chip/Chiplet chassis concepts: clock and reset, power and thermal management, out-of-band management, platform security, RAS, debug & test, eFuse control and distribution, and related areas.
• Expertise in designing with Verilog, System Verilog, Perl, and Tcl scripts.
• Proficiency with EDA tools (e.g., VCS, Design Compiler).
• Experience with Front End activities and quality checks (e.g., Lint, CDC).
• Good understanding of DV, DFT, and timing closure.
• Ability to provide timing constraints and collaborate with PD teams to ensure RTL meets timing.
• Strong debugging and scripting skills (Perl, Python, Tcl).

• Salary range: $190,000 – $270,000.
• Employee may be eligible for performance bonuses and short/long-term incentive programs. Total compensation depends on skills, experience, and qualifications.
• Benefits include health, life and disability insurance, savings plan, company-paid holidays, sick leave, vacation, parental leave, 401(k), and more.
• Media Tek is an Equal Opportunity Employer committed to inclusion and diversity for all, regardless of age, ancestry, color, disability, gender identity, genetic information, marital status, medical condition, military or veteran status, national origin, race, religion, sex, sexual orientation, and other legally protected characteristics.