Intern - Characterization and Support

Overview

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. This is an on‑site internship role in San Jose, California, within the Cadence DDR IP group for a Post‑Silicon Validation Engineering Intern.

• Validate both system‑level and electrical performance of internal silicon test chips.
• Debug silicon issues in close collaboration with analog and digital design teams.
• Deliver high‑quality characterization reports.
• Work cross‑functionally to ensure product functionality, reliability, and successful deployment.

• Current Bachelor’s or master’s degree in electrical engineering with 0‑2 years of relevant work experience.
• Very good fundamentals in analog and digital electronics, RTL, signal integrity, and control systems.
• Strong analytical and problem‑solving skills.
• Excellent written and verbal communication skills.
• Ability to work collaboratively in a team environment.
• Prior experience in the hardware semiconductor or electronics industry is a plus.
• Experience with script‑based test automation in Python, C, or other scripting tools is a plus.

Cadence is committed to equal employment opportunity throughout all levels of the organization.