Staff Engineer, FPGA

Please Note:

To provide the best candidate experience amidst our high application volumes, each candidate is limited to 10 applications across all open jobs within a 6-month period.

Our technology solutions power the tools you use every day--including smartphones, electric vehicles, hyperscale data centers, IoT devices, and so much more. Here, you’ll have an opportunity to be part of a global leader whose innovative designs are pushing the boundaries of what’s possible and powering the future.

We believe innovation and growth are driven by an inclusive culture and a diverse workforce. We’re dedicated to empowering people to be their true selves. Together, we’re building a better tomorrow for our employees, customers, partners, and communities.

Daily onsite presence at our San Jose, CA office / U.S. headquarters in alignment with our Flexible Work policy.

• RTL Design & Architecture:
  Develop and optimize RTL (System Verilog/Verilog) IPs for CXL Type-2 FPGAs, focusing on the CXL.cache controller, command queues and DMA management.
• Command Queue Management:
  Design high-speed, cache-line-granular command queue interfaces to allow host CPUs to efficiently update device registers and control structures.
• CXL Cache Coherency:
  Implement hardware mechanisms to maintain coherent access between host CPU and FPGA, reducing synchronization latency and software overheads.
• Performance Optimization:
  Optimize RTL to meet strict latency and bandwidth requirements, managing memory access patterns and improving the pipeline for high-speed operations.
• System Integration & Debug:
  Collaborate with software engineers to integrate with kernel drivers and user-space libraries. Debug complex RTL-to-Host issues in a laboratory environment, using tools like logic analyzers, PCIe protocol analyzers, and CXL emulators.
• Verification:
  Develop System Verilog test benches and simulation models to verify protocol compliance and functional correctness, focusing on high-speed data processing.

• Bachelor’s with 10+ years, or Master’s with 8+ years, or PhD’s with 5+ years of industry experience.
• BS/MS in Electrical Engineering, Computer Engineering, or related field with 3-5+ years of industry experience in FPGA development, with a strong portfolio in high-performance digital design (More experienced candidates will also be considered at relevant levels).
• Expertise in System Verilog, Verilog, and RTL design tools such as Xilinx Vivado, Intel Quartus and familiarity with simulation tools such as Questa, Xcelium, or VCS.
• Strong computer architecture, memory coherency, and data structures fundamentals.
• Deep understanding of AMBA (AXI/AXIS), PCIe, CXL.cache protocols and CXL Type-1/2 devices.
• Prior experience in designing coherent memory systems and control path design for accelerators is a big plus.
• Strong analytical and troubleshooting skills to resolve complex hardware bottlenecks.
• Must be highly motivated with excellent verbal and written communication skills, and ability to thrive in a collaborative, multi-disciplinary environment.

The pay range below is for all roles at this level across all US locations and functions. Pay within this range varies by work location and may also depend on job-related knowledge, skills, and experience. We also offer incentive opportunities that reward employees based on individual and company performance.

With a charitable giving match and frequent opportunities to get involved, we take an active role in supporting the community.

You’ll start with 4+ weeks of paid time off a year, plus holidays and sick leave, to rest and recharge.

Whatever family means to you, we want to support you along the way – including a stipend for fertility care or adoption, medical travel support, and virtual vet care for your fur babies.

With on-demand apps and free confidential therapy sessions, you’ll have support no matter where you are.

Eating well and being active are important parts of a healthy life. Our onsite Cafe and gym, plus virtual classes, make it easier.