ASIC/SoC Design Verification Engineer
Listed on 2026-06-18
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Engineering
Test Engineer, Hardware Engineer
Responsibilities
- Collaborate with design engineers and architects to define, document and implement detailed test plans for the SoC design verification
- Build and maintain infrastructure/environment for automation verification of SoC architecture, function and performance
- Develop reusable testbench, constrained-random/directed test cases, and verification associated behavioral module for both block levels and system levels
- Develop regression strategy, methodology and tools (scripts). Define and measure the function coverage. Close verification holes for design releases and tape-out
- Work with design engineers to debug and identify root causes of simulation failure
- Support test engineers for post-silicon validation
- Mentor and coach team members and junior engineers. Drive verification efficiency
- MS with 8+ years of relevant experience or PhD (with 3+ years of experience) in Electrical Engineering, Computer Engineering, Computer Science or related degree
- In depth knowledge of UVM/OVM, Semi formal Verification, assertion-based verification as well as hardware and software co‑verification methodology
- Extensive experience of building verification infrastructure, test planning, coverage closure, testbench and test cases development for function/performance verification
- Proficient experience with Verilog, System Verilog, Python/Perl/TCL/Shell scripting, C/C++, System C and industry mainstream ISAs assembly coding
- Familiarity with MIPI, AMBA (APB/AHB/AXI) bus protocol, RISC‑V/ARM or DSP core
- Experience in verifying designs at both RTL level and post‑P&R gate level
- Ability to work in a startup environment, and to work both independently and as a team player with the ability to provide technical leadership to other members of the engineering team
- Working knowledge of AI/ML Computing, GPU, ISP architectures and accelerators
- Experience in verifying mix-signal design and interface of digital and analog
- Experience of design verification for highspeed IO such as PCIE and DDR
$110,000 - $300,000 / year
Tetra Mem celebrates diversity and is committed to creating an inclusive environment for all employees. We are proud to be an Equal Opportunity Employer and welcome applicants from all backgrounds. Qualified candidates will receive consideration for employment without regard to race, color, religion, creed, sex, gender identity or expression, sexual orientation, national origin, ancestry, age, marital status, medical condition, disability, genetic information, military or veteran status, or any other characteristic protected by applicable federal, state, or local law.
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