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Sr Principal AE - Emulation

Job in San Jose, Santa Clara County, California, 95199, USA
Listing for: Cadence Design Systems, Inc.
Full Time position
Listed on 2026-06-18
Job specializations:
  • Engineering
    Hardware Engineer
Salary/Wage Range or Industry Benchmark: 125000 - 150000 USD Yearly USD 125000.00 150000.00 YEAR
Job Description & How to Apply Below

As an integral member of the North America Verification Field Applications Engineering (AE) Team, you will work directly with industry‑leading semiconductor and system companies to deploy Cadence’s market‑leading Emulation and FPGA Prototyping platforms, Palladium and Protium. In this customer‑facing role you will provide the front‑line technical support in the pre‑ and post‑sales process and collaborate with account team members to deliver innovative solutions for our customers’ emulation and prototyping needs.

Responsibilities
  • Establish technical credibility and rapport with the customer and become the go‑to expert for all technical inquiries and support.
  • Provide in‑depth technical assistance in collaboration with R&D to support advanced verification flows and secure design wins.
  • Champion customer needs and work with R&D and marketing to develop competitive and creative technical solutions.
  • Understand the competitive landscape and work to differentiate Cadence’s solutions.
  • Write technical product literature such as application notes and technical articles.
  • Review new product proposals and device specifications.
  • Assume technical leadership roles within the team as needed.
Requirements – Mandatory
  • 5+ years of industry experience.
  • Experience in hardware acceleration, in‑circuit emulation, or FPGA prototyping.
  • MS or PhD degree in Computer Science, Engineering, or related field.
  • Strong RTL and testbench debug skills.
  • Experience with synthesizable coding style.
  • Experience writing scripts (Perl, Python, or TCL).< /li>
  • Strong software, HDL design, and verification skills.
  • Experience with System Verilog, VHDL, Verilog, C/C++, or System

    C.
  • Ability to quickly analyze verification environments and design complexity.
  • Strong verbal and written communication skills.
  • Strong teamwork skills.
  • Ability to interact effectively with external customers and R&D teams.
Preferred
  • Experience with multiple clock domains and asynchronous interfaces.
  • Knowledge of the FPGA development process and tool flow from RTL to bitstream for Xilinx and/or Altera products.
  • Hands‑on experience with lab bring‑up, debug, chipscope, and instrument usage.
  • Experience with C/C++/System

    C.
  • Knowledge of fundamental SoC architecture.
  • Understanding of embedded software development and HW/SW co‑design/co‑verification.
  • Knowledge of protocols such as JTAG, UART, PCIe, AMBA, DDR, and CHI.
  • Knowledge of design fundamentals such as architecture, micro‑architecture, HDLs, synthesis, and timing.

Cadence is committed to equal employment opportunity throughout all levels of the organization.

Cadence participates in the E‑Verify program in certain U.S. locations as required by law.

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