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Senior FPGA RTL Engineer: CXL Cache Perf
Job in
San Jose, Santa Clara County, California, 95199, USA
Listed on 2026-06-18
Listing for:
Samsung Semiconductor
Full Time
position Listed on 2026-06-18
Job specializations:
-
Engineering
Test Engineer, Electronics Engineer, Hardware Engineer
Job Description & How to Apply Below
Samsung Semiconductor is seeking an experienced RTL Design Engineer at our San Jose, CA office to develop and optimize RTL for CXL Type-2 FPGAs, focusing on command queues and DMA management.
The role requires extensive industry experience, strong skills in System Verilog and Verilog, and proficiency in FPGA development. The pay range for this position is $163,000—$253,000 USD, along with comprehensive benefits.
#J-18808-LjbffrPosition Requirements
10+ Years
work experience
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