ASIC Synthesis & Timing Engineer

Overview

As a member of the ASIC Implementation team, you will be part of the team implementing new technologies in a variety of exciting consumer electronic devices. You will be directly involved in:

• Leading a Synthesis and Timing of complex designs, provide guidance, interface with RTL team for quality RTL delivery
• Full chip and Block constraints development and constraints generation.
• Full chip and Block Synthesis, STA and timing closure
• Interfacing with internal external teams including Design, IP, Library
• Methodology & Flow development of Synthesis, Formality, STA, Low power checks & Timing Closure
• Working independently with the PNR & RTL design team on Physical implementation and Power-intent requirements

• BS+ 15 or MS+ 12 Years in
  
  E.E
• Should have done multiple Tapeouts, have extensive experience in frontend tools such as Primetime, DC, VCLP, Formality, UPF, LEC, Timing closure and timing
• Extensive knowledge of PT/DC is important. Good in TCL scripting.