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Senior Design Verification Engineer
Job in
San Jose, Santa Clara County, California, 95199, USA
Listed on 2026-06-18
Listing for:
Canvendor
Full Time
position Listed on 2026-06-18
Job specializations:
-
Engineering
Test Engineer, Hardware Engineer, Electronics Engineer
Job Description & How to Apply Below
We are seeking a Design Verification Engineer to join our Interface IP DV team. You will work with architects, designers, and vendors to ensure that all our architecture requirements are met in the IP subsystems and interfaces being created, validate correctness and performance across the full hardware-software stack. This role demands creativity, deep technical ability, and the drive to tackle complex verification challenges.
Keyresponsibilities
- End to end ownership of one or more of the following IP subsystems: PCIe, Ethernet, CPU (arc/arm), low power peripherals, sensors
- Develop and maintain UVM/System Verilog-based verification environments to ensure functional correctness, performance, and compliance with IP specifications.
- Collaborate with integration and SoC DV teams to validate seamless interaction of external IPs within the broader chip architecture.
- Drive coverage closure and sign-off by defining metrics, analyzing gaps, and
- ensuring comprehensive verification across corner cases and stress scenarios
Position Requirements
10+ Years
work experience
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