More jobs:
Hybrid Principal Verification Engineer — Lead Chip UVM
Job in
San Jose, Santa Clara County, California, 95199, USA
Listed on 2026-06-18
Listing for:
OSI Engineering
Full Time
position Listed on 2026-06-18
Job specializations:
-
Engineering
Test Engineer, Hardware Engineer
Job Description & How to Apply Below
A leading chip and silicon IP provider is seeking a Principal Verification Engineer in San Jose, CA. This full-time hybrid role involves leading verification strategies and working alongside talented engineers. Candidates should have extensive experience in System Verilog and UVM, with a strong background in ASIC verification tools. The position offers a salary range of $170,000 – $196,000 based on experience.
#J-18808-Ljbffr
To View & Apply for jobs on this site that accept applications from your location or country, tap the button below to make a Search.
(If this job is in fact in your jurisdiction, then you may be using a Proxy or VPN to access this site, and to progress further, you should change your connectivity to another mobile device or PC).
(If this job is in fact in your jurisdiction, then you may be using a Proxy or VPN to access this site, and to progress further, you should change your connectivity to another mobile device or PC).
Search for further Jobs Here:
×