Design Engineer

Responsibilities

Use physical design expertise to implement challenging designs in 2nm/3nm/5nm technology nodes. Hands‑on experience in netlist→gds implementation of multimillion‑gate designs, including floor planning, placement & routing, STA, and physical verification (LVS, DRC, ANT, ERC). Work closely with designers and write TCL scripts to perform custom/semi‑custom standard‑cell placement, clock‑tree adjustments, and routing to achieve design specifications. Good timing analysis and CTS knowledge are required.

Full chip assembly and spice‑simulation experience is a plus.

• MSEE/MSCS 6+ years (or BSEE/BSCS 8+ years)
• Expertise in Cadence Innovus/Atop physical‑design tools
• Experience with Calibre LVS/DRC
• Collaborate closely with RTL & DFT designers
• Strong TCL/Python scripting knowledge (Perl a plus)
• Excellent debugging skills and ability to work around issues
• Tape‑out experience and a good team player
• Hands‑on experience in hierarchical top‑level floor planning, IO ring design, placement & routing, clock‑tree building, and STA (preferred)

• Annual base salary range: $120,000 – $192,000
• Discretionary annual bonus eligibility
• Competitive new‑hire equity grant and annual equity awards
• Medical, dental and vision plans
• 401(k) participation with company matching
• Employee Stock Purchase Program (ESPP)
• Employee Assistance Program (EAP)
• Paid holidays, sick leave and vacation time
• Paid Family Leave and other leaves of absence as required by law

Broadcom is a proud equal‑opportunity employer. We will consider qualified applicants without regard to race, color, creed, religion, sex, sexual orientation, national origin, citizenship, disability status, medical condition, pregnancy, protected veteran status or any other characteristic protected by federal, state, or local law. We will also consider qualified applicants with arrest and conviction records consistent with local law.