Principal Analog IC Design Engineer, Speed SerDes

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

The Principal Analog IC Designer is responsible for the design and development of analog/mixed signal IC circuit blocks from initial concept/specification through final verification of conformance to customer specifications.

• Minimum 7 years of experience in CMOS Ser Des or high‑speed I/O IC design and development.
• Working knowledge of common Ser Des standards and electrical requirements.
• Thorough understanding of jitter and signal equalization techniques.
• Proficient design experience in most of the following Ser Des circuit blocks:
  Driver;
  Receiver;
  Serializer;
  Deserializer;
  Phase Interpolator;
  Low jitter PLL;
  High Speed Clock Distribution; ADC and DAC;
  Bias and Bandgap; and Voltage Regulators.
• Excellent problem solving skills, analog aptitude, good communication skills, and ability to work cooperatively in a team environment.
• Proficiency in using CAD tools for circuit simulation, layout, and physical verification.
• Cadence tool experience, lab test experience, and design experience at >10 Gbps and in