Product Development Engineer

About Altera

Altera has been at the forefront of programmable logic technology for decades. Our commitment to innovation has empowered countless customers to create groundbreaking solutions that have transformed industries. We are working towards becoming the #1 FPGA company.

The Product Development Team is responsible for performing silicon failure and yield analysis to optimize RISO and PRQ goals. We support wafer yield ramp and fab process optimization in the early production stage for wafer sort and class yield through systematic test data analysis to isolate and mitigate defects and failures.

We are seeking a motivated Product Development Engineer to assist in the following areas (not limited to):

• Drive and develop testability and manufacturability of integrated circuits from component debug feasibility through production ramp.
• Contribute to performing yield analysis to identify yield‑limiting issues using data science, analytics and machine learning techniques to isolate failures faster.
• Interface with fabrication, sort, assembly, component debug, test program developers, failure analysis, quality and reliability, and manufacturing groups to enable healthy silicon and on‑time PRQ.
• Identify root cause of systematic yield issues by applying test program/pattern skills and propose mitigation plan within a defined timeline to support PRQ.
• Perform ATE device characterization, utilize the data to define datasheet specifications and perform yield analysis.
• Maintain up‑to‑date Yield Dashboard & KPI to identify yield issues and communicate to stakeholders and management.
• Develop new yield modeling methods and AI algorithms using machine learning to deliver world‑class yield predictability.
• Advance knowledge and understanding of FPGA architecture/design, fab process, test program/content, sort and class defects, and their root causes to solve problems faster.
• Develop and debug complex test programs/patterns to convert design validation vectors and resolve silicon‑level yield limiters.
• Ensure manufacturability over process and product design through thorough analysis of process and spec corners and work with design to resolve yield issues before manufacturing ramp.

The pay range below is for Bay Area California only. Actual salary may vary based on a number of factors including job location, job‑related knowledge, skills, experiences, trainings, etc. We also offer incentive opportunities that reward employees based on individual and company performance.

$142, USD.

Minimum Qualifications

• Bachelor’s degree in Electrical Engineering or a related field.
• 7+ years of industry experience in Yield Engineering, Test Engineering, or Silicon Manufacturing Engineering for advanced semiconductor products.

Preferred Qualifications

• Master’s degree or PhD in Electrical Engineering or a related field.
• 5+ years of industry experience in Yield Engineering, Test Engineering, or Silicon Manufacturing Engineering for advanced semiconductor products.

Regular.

Shift 1 (United States of America).

San Jose, California, United States.

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.