Senior SerDes Engineer Speed I/O & Analog Blocks
Job in
San Jose, Santa Clara County, California, 95199, USA
Listed on 2026-06-18
Listing for:
Cadence
Full Time
position Listed on 2026-06-18
Job specializations:
-
Engineering
Systems Engineer, Electronics Engineer, Hardware Engineer, Electrical Engineering
Job Description & How to Apply Below
Cadence in San Jose is seeking a Principal Analog IC Designer to lead the design and development of analog/mixed signal IC circuit blocks. Candidates must have a minimum of 7 years of experience in CMOS Ser Des or high-speed I/O IC design and development.
The role involves designing and verifying IC block specifications using advanced CAD tools. A strong educational background, excellent problem-solving skills, and proficiency in signal integrity techniques are essential. The position offers a salary range between $136,500 and $253,500 and a variety of benefits.
#J-18808-LjbffrPosition Requirements
10+ Years
work experience
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