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Project Design Lead; EX

Job in San Jose, Santa Clara County, California, 95199, USA
Listing for: Nexperia
Full Time, Part Time position
Listed on 2026-06-18
Job specializations:
  • Engineering
    Systems Engineer, Electronics Engineer, Hardware Engineer, Test Engineer
Salary/Wage Range or Industry Benchmark: 188760 USD Yearly USD 188760.00 YEAR
Job Description & How to Apply Below
Position: Project Design Lead (EX)

Overview

Nexperia is a world-class company in semiconductor development and in-house production. A proven global player with an entrepreneurial mentality. At our core is a 13,000+ strong international network with a singular focus. Built on passion and commitment to our work, belief in our goals and a drive to succeed regardless of the challenges we face. We support, reward and challenge individuals equally, in a dynamic and energetic environment.

Role

Project Design Lead, Nexperia USA Inc., San Jose, CA
:
Design digital logic circuits for integration into mixed-signal ICs, including finite state machines, control logic, data path components, and interface blocks, based on product requirements and system architecture specifications. Perform static design verification including Lint checking to ensure code quality, Clock Domain Crossing (CDC) analysis to validate synchronization of asynchronous clocks and Reset Domain Crossing (RDC) analysis to confirm correct handling of resets across domains.

Analyze simulation, synthesis, and timing reports to validate design quality and correct operation under different process-voltage-temperature (PVT) conditions. Conduct applied research into machine learning (ML) or artificial intelligence (AI) techniques for the purpose of improving digital design and verification flows, including automation of test generation, design space exploration, and bug triage. Translate system and product definition documents into digital architecture, block-level specifications, and micro-architecture definitions, and document digital design implementation details.

Generate behavioral models of analog or mixed-signal components using high-level modeling techniques (e.g., System Verilog, Verilog-A) to enable mixed-signal simulation and validate digital-analog interaction early in the design process. Build Field Programmable Gate Array (FPGA) prototypes for digital logic emulation, perform functional tests using application-level scenarios, and collaborate with firmware teams for pre-silicon validation and debugging. Participate in post-silicon bring-up by analyzing lab measurements and test data, identifying root causes of issues, comparing silicon behavior with simulation models, and recommending fixes or design changes.

Develop scripts, ML models, or AI-based tools to optimize verification workflows, automate debugging tasks, extract features from simulation datasets, and enhance RTL code quality and coverage metrics. Collaborate with cross-functional teams including analog designers, system engineers, software developers, and CAD/methodology engineers to define requirements and integrate AI-enhanced solutions into production design workflows.

Qualifications

Employment type and compensation
:
Full time employment, Monday – Friday, 40 hours per week, $188,760 per year.

Minimum Requirements

Must have a Master’s degree in Electrical Engineering, Computer Engineering, or a related field and 2 years of experience in digital IC design and verification. Alternatively, a Bachelor’s degree and 4 years of experience. Must have 2 years of experience in each of the following:

  • Experience with digital circuit design and verification for mixed-signal chip products
  • Experience using simulation tools, including Cadence Xcelium, to debug RTL and analyze RTL code coverage
  • Experience working in at least one project in verification environment and platform setup
  • Experience working in at least one project in digital function design
  • Experience with RTL design using Verilog or System Verilog
  • Experience with static design checks including Lint, CDC, and RDC
  • Experience with FPGA prototyping and pre-silicon validation
  • Experience with post-silicon debugging
  • Experience using AI/ML tools in digital design automation

Telecommuting permitted up to 3 days per week.

Nexperia is an Equal Opportunity Employer that does not discriminate on the basis of race, color, creed, religion, national origin, ancestry, citizenship status, age, sex or gender (including pregnancy, childbirth and pregnancy-related conditions), gender identity or expression, sexual orientation, marital status, military service and veteran status, physical or mental disability, genetic information, or any other characteristic protected by applicable laws. Nexperia’s management is dedicated to this policy with respect to recruitment, hiring, placement, promotion, transfer, training, compensation, benefits, and general employment practices.

D&I Statement As an equal-opportunity employer, Nexperia values diversity and is committed to inclusive recruitment and a safe work environment. We support employee resource groups.

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