PLL Design Engineer — On-site, -Speed CMOS
Job in
San Jose, Santa Clara County, California, 95199, USA
Listed on 2026-06-18
Listing for:
Celero Communications, Inc.
Full Time
position Listed on 2026-06-18
Job specializations:
-
Engineering
Systems Engineer, Electrical Engineering, Electronics Engineer
Job Description & How to Apply Below
Celero Communications, Inc. is seeking a High-Speed CMOS PLL Analog Design Engineer in San Jose, CA. This pivotal role involves working on advanced optical transceiver technologies, focusing on PLL design and performance characterization.
The ideal candidate will have a Master’s or PhD in Electrical Engineering, extensive experience in PLL design, and proficiency with tools such as Cadence Virtuoso and MATLAB. The position offers an annual salary ranging from $150,000 to $250,000, depending on skills and experience.
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