Senior Digital Design Engineer

We’re looking for a Senior Digital Design Engineer to lead front-end ASIC design efforts, including architecture, implementation, and verification of complex logic blocks. You’ll collaborate across design, verification, and physical teams to ensure successful tape-outs, while contributing to microarchitecture specs, IP integration, and chip bring-up. This role combines technical depth with cross‑functional teamwork to deliver high‑performance digital solutions.

Base salary range is $140,000 - $170,000 a year. The base salary offer will depend on factors such as education, experience, training, skills, qualifications, and location. This position is also eligible for a discretionary bonus, equity and a full range of medical and other benefits.

• Purpose: We invest in what matters. From meaningful‑future shaping projects to competitive compensation, we empower you to grow your career while making a lasting impact.
• People: Connection starts within. We collaborate, celebrate wins, and create an environment where everyone can do their best work.
• Possibilities: Our belief shapes what’s next. Our technology powers the most reliable and energy‑efficient connections around the world – and our team powers new products and markets that come next.

• Write microarchitecture and/or design specifications.
• Architect/design, implement, and debug complex logic blocks.
• Understand and integrate complex IPs from internal and external IP vendors.
• Support all front‑end integration activities like Lint, CDC, Synthesis, and ECO.
• Develop functional tests/test benches and run functional RTL and Gate‑Level verification/simulations.
• Work with other ASIC Design/Verification, DFT and Physical Design Engineers in achieving a successful tape out.
• Collaborate with Software, Firmware, Applications, and Systems teams to ensure a high‑quality product.
• Bring‑up, validate, and debug functional features in the chip.

• BS or MS in Electrical Engineering, Computer Engineering, or related field with 5–10 years of experience in digital ASIC design
• Strong understanding of digital logic design, including synchronous and asynchronous interfaces
• Proficiency in Verilog/System Verilog RTL design
• Experience developing test benches and test cases for block‑level and top‑level verification
• Familiarity with UVM methodology
• Hands‑on experience with gate‑level simulations, chip bring‑up, and validation
• Knowledge of synthesis and static timing analysis
• Proficiency in scripting languages such as Python, Tcl, Perl, or Shell
• Strong planning and estimation skills
• Effective communicator and collaborative team player

Credo’s mission is to transform connectivity at scale through fast, reliable, and energy‑efficient system solutions. Our high‑speed copper and optical interconnect products deliver industry‑leading power and performance at up to 1.6T to meet the ever‑expanding data infrastructure demands of AI.

Our product portfolio includes Zero Flap (ZF) Active Electrical Cables (AECs) and ZF optical transceivers, Omni Connect memory solutions, and a suite of retimers and DSPs for optical and copper Ethernet and PCIe, all leveraging the PILOT diagnostic and analytics software platform. Credo innovations enable our customers to connect the systems that connect the world.

Credo is committed to creating an inclusive environment for all employees and welcome applicants from diverse backgrounds without regard to race, color, religion, gender, sex, sexual orientation, national origin, genetic information, age, disability, veteran status, or any other legally protected basis. If you have a disability or special need that requires accommodation to navigate our website or complete the application process, email