R&D Digital Design Engineer Job San Jose area,California USA,Engineering

The CSG group at Broadcom has brought some of the most complex and cutting‑edge networking ASICs and multi‑chip solutions to market over the last decade. The group develops Tomahawk ASICs for scale‑out and scale‑up AI networks. These products support the latest networking protocols and features as well as manage extremely large volumes of traffic on the order of several hundreds of terabits per second.

The ASICs support a large number of ports ranging from 10/100 Mb/s to 1600 Gb/s speeds as well as various line interfaces and protocols.

Responsibilities

Participate in the verification processes of L2/L3 network switching and routing ASICs and various subsystems within these chips.

Understand the architecture and implementation of these chips and develop in‑depth test plans for verifying key networking features such as L2/L3 traffic streaming, traffic management, scheduling and shaping, and latency and performance characterization of chips and systems.

Develop verification environments, including test benches and verification APIs associated with the chip architecture, and prepare scripts and Makefiles as required to run the environment in various tool chains.

Implement test plans into executable test suites using a cutting‑edge System Verilog verification environment.

Execute the verification process to completion pre‑silicon, using various functional and code‑coverage metrics as measures of completion.

Qualifications

Graduate degree (MSEE/BSEE or equivalent) in digital design with excellent academic standing. Minimum experience requirements:
Bachelor’s degree + 8 years, Master’s degree + 6+ years, PhD + 3+ years, or equivalent.

Familiarity with hardware description languages (Verilog/System Verilog/UVM), scripting languages (Perl, Python), and object‑oriented programming.

Experience with cutting‑edge verification and validation techniques, using object‑oriented modular reusable environments in System Verilog, Perl, and Python.

Strong understanding and prior experience of end‑to‑end verification processes from test‑plan definition to coverage closure on ASIC/SOC silicon that has entered mass production.

Excellent verbal and written communication skills.

Compensation and Benefits

The annual base salary range for this position is $121,900 - $195,000. Eligible for a discretionary annual bonus and competitive new‑hire equity grant, as well as annual equity awards. Broadcom offers a comprehensive benefits package, including medical, dental, and vision plans; 401(K) participation with company matching;
Employee Stock Purchase Program (ESPP);
Employee Assistance Program (EAP); company‑paid holidays, paid sick leave, and vacation time; and compliance with applicable laws for paid family leave and other leaves of absence.

Equal Opportunity Employer

Broadcom is proud to be an equal‑opportunity employer. We will consider qualified applicants without regard to race, color, creed, religion, sex, sexual orientation, national origin, citizenship, disability status, medical condition, pregnancy, protected veteran status or any other characteristic protected by federal, state, or local law. We will also consider qualified applicants with arrest and conviction records consistent with local law.

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