Integrated Circuit Verification Engineer

H1B assistance and Canadian VISA support is available.

Boston or Santa Clara

Memory-to-Compute Fabric for LLM Data Centers.

Optimum verification methodology.

The work involves learning advanced LLM in modern data centers and applications to design memory acceleration.

• Excellent leadership.
• Strong knowledge across the full ASIC/SOC development cycle from microarchitecture development to tape‑out in advanced process technologies.
• Outstanding technical expertise in verification methodologies.
• Hands‑on design experience in one or more industry standards/protocol stacks such as Ethernet, UCIe, UALink etc.
• Demonstrated ability to optimize designs for PPA (power, performance, area) and to integrate major subsystems (interconnect, I/O, memory).
• Proficiency with front‑end development tools/methodologies, and scripting for automation and flow integration.
• Verification and tape‑out of any advanced silicon device is highly preferred.
• Post‑Silicon validation of any silicon ASIC/SoC is highly preferred.

• PhD in Electrical Engineering, Computer Engineering, or a related field.
• Experience managing relationships with external design partners, IP vendors, and foundries.
• Knowledge of Design‑For‑Testability, post silicon debug/validation/manufacturing test.