Micro-architect​/Logic Designer, Coherent Interconnect

Position Summary

Samsung, a world leader in advanced semiconductor technology, is founded on a simple philosophy – the endless pursuit of excellence will create a better world for all. At Samsung Austin Research and Development Center (SARC) and Advanced Computing Lab (ACL), we are building a center of excellence for Intellectual Property (IP) that is applied to high-performance computing devices consumed by millions of people around the world.

Come build with us!

As a Micro-Architect/Logic Designer, you will be responsible for leading the micro-architecture development of custom coherent interconnect IP and last-level cache blocks. In this role you will interact with system architects, verification, performance/power, and design implementation teams. You will own and drive the critical coherent interconnect related RTL design, performance and power optimization, and also work on logic debug and timing closure of the design.

• Drive the timely development of custom coherent interconnect IP and/or last-level cache blocks.
• Partner with architects to define next-generation Samsung coherent interconnects and LLC.
• Perform microarchitecture development and specification – from early high-level architectural exploration through micro-architectural research to a detailed specification.
• Work alongside the verification team to verify the functionality and correctness of the design.
• Collaborate with implementation to achieve timing and area goals.
• Produce quality RTL on schedule meeting PPA goals.
• Engage with performance and power team to achieve performance and power goals.
• Work with the physical design and CAD team to resolve implementation level details.
• Help mentor junior engineers in the team.

• 10+ years of experience with a Bachelor’s degree in Computer Science/Computer Engineering/relevant technical field, or 8+ years of experience with a Master’s degree, or 6+ years of experience with a PhD.
• Strong background owning and driving the RTL design of various sub-blocks of the coherent interconnect or memory controller or LLC for high-performance digital designs.
• Demonstrated successful architectural through RTL design experience on high-performance digital designs.
• Verilog expertise is required, as is a deep understanding of ASIC design flow including RTL design, verification, logic synthesis, prototyping, DFT, timing analysis, floor-planning, ECO, bring-up & lab debug.
• Knowledge of system caches and directory snoop filter protocols.
• Familiarity with different on-chip network topologies: mesh, ring, crossbar.
• Experience in leading and mentoring a team of engineers.
• Knowledge of ARM AMBA5 CHI, AMBA4 ACE or AXI coherent interconnect and bus protocols.
• Knowledge of memory subsystem design including coherent cache design.
• Strong communication and interpersonal skills are required, along with the ability to work in a dynamic, global team.

• Knowledge of Verilog/VHDL, scripting, STA, DFT, ECO flows.
• Proficient in AMBA, ACE, AXI, CHI protocols.
• Knowledge of coherent interconnect, memory controller, and/or cache design.
• Knowledge of memory subsystem, coherency, directory snoop filter protocols.
• Familiarity with different on-chip network topologies: mesh, ring, crossbar.
• Experience with a scripting language like Perl or Python.

At Samsung – SARC/ACL, base pay is one part of our total compensation package and is determined within a range. The base pay range for this role is between $151,000 and $251,800. Your actual base pay will depend on variables that may include your education, skills, qualifications, experience, and work location. This is an exempt position, which is not eligible for overtime pay under the Fair Labor Standards Act (FLSA).

Samsung employees have access to benefits including medical, dental, vision, life insurance, 401(k), free onsite lunch, employee purchase program, tuition assistance (after 6 months), paid time off, student loan program, wellness incentives, and many more. In addition, regular full-time employees (salaried or hourly) are eligible for MBO bonus compensation, based on company, division, and individual performance.…