Senior ASIC Design Engineer in San Jose

Job in San Jose, Santa Clara County, California, 95199, USA

Listing for: Energy Jobline ZR

Full Time position
Listed on 2026-06-19

Job specializations:

Engineering
Hardware Engineer, Test Engineer, Systems Engineer, Electronics Engineer

Salary/Wage Range or Industry Benchmark: 125000 - 150000 USD Yearly USD 125000.00 150000.00 YEAR

Position:
Senior ASIC Design Engineer

Location:

San Jose

What We Offer

Opportunity to work on cutting-edge AI-SSD architecture
High-impact role in next- storage innovation
Collaborative and fast-paced engineering culture

Responsibilities

Contribute to the microarchitecture design of next-SSD controllers and storage subsystems, with a focus on optimizing architectures for AI applications.

Develop and write detailed design specifications, microarchitecture documents, and implementation guidelines.

Design and implement key functional blocks using Verilog/System Verilog RTL.

Work closely with the verification team to define test plans, coverage analysis, and support full-chip simulation, debug, and validation.

Collaborate with the physical design team to ensure timely and high-quality RTL-to-GDS implementation.

Support post-silicon bring-up, debugging, and performance validation in the lab.

Work closely with firmware and system teams to ensure feature alignment and product-level performance targets are met.

Perform design analysis and optimization to improve performance, power efficiency, and area (PPA).

Qualifications

Bachelor’s degree or above in Electrical Engineering, Computer Engineering, Computer Science, or related fields.

3+ years of ASIC design experience, preferably in storage or high-performance SoC design.

Strong understanding of the full ASIC design flow, including both front-end and back-end processes.

Solid experience in digital design and RTL development, with proficiency in Verilog/System Verilog.

Familiarity with at least one scripting/programming (e.g., Python, Tcl, Perl, Shell).

Strong problem‑solving skills, self‑motivated, and able to work effectively in a collaborative team environment.

Experience in SSD controller or storage system design.

Familiarity with AI/ML workload acceleration, memory/storage hierarchy, or data path optimization.

Hands‑on experience with synthesis (Design Compiler), STA, CDC, lint, and formal verification flows.

Knowledge of UVM-based verification methodologies.

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