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Senior Analog Layout Engineer – RF​/SerDes; 7nm​/5nm

Job in San Jose, Santa Clara County, California, 95199, USA
Listing for: Technical Link LLC
Full Time position
Listed on 2026-06-19
Job specializations:
  • Engineering
    Electronics Engineer, Systems Engineer, Electrical Engineering, Hardware Engineer
Salary/Wage Range or Industry Benchmark: 100000 - 125000 USD Yearly USD 100000.00 125000.00 YEAR
Job Description & How to Apply Below
Position: Senior Analog Layout Engineer – RF/SerDes (7nm/5nm)

Technical Link LLC is seeking an Analog and Mixed-Signal Layout Engineer in San Jose, California. The role involves independent Analog layout design and collaboration with engineers for high-frequency analog circuits.

Ideal candidates will have a Bachelor’s degree and extensive experience in advanced analog layout, specifically in Fin Fet technologies. Proficiency with Cadence Virtuoso and ESD concepts is required, along with excellent communication skills to work within a diverse team.

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Position Requirements
10+ Years work experience
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