Application Engineering Director - IC Design Verification

Responsibilities

• Establish technical credibility and rapport with customers, becoming the go‑to expert for all technical inquiries and support.
• Collaborate with R&D to provide in-depth technical assistance, supporting advanced verification flows and AI/ML applications.
• Champion customer needs and work with R&D and marketing to develop competitive and creative technical solutions.
• Understand the competitive landscape and continually differentiate Cadence solutions.

• BS, MS, or PhD in Computer Science/Engineering, Electrical Engineering, or a related field.
• 15+ years of experience in the semiconductor industry.
• Strong understanding and working knowledge of System Verilog, Verilog, and UVM testbench architecture.
• Excellent verbal and written communication skills.
• Digital design experience and knowledge of design fundamentals such as architecture and micro‑architecture.
• Ability to interact effectively with external customers and internal AE and R&D teams.

The annual salary range for California is $157,500 to $292,500. Incentive compensation may include bonus, equity, and benefits. Employees receive paid vacation, paid holidays, a 401(k) plan with employer match, an employee stock purchase plan, and various medical, dental, and vision plans.

Cadence is committed to equal employment opportunity throughout all levels of the organization. All qualified applicants will receive consideration for employment without regard to race, color, sex, age, national origin, religion, sexual orientation, gender identity, status as a veteran, basis of disability, or any other protected class.