Intern - Characterization and Support

Overview

Cadence is seeking a Post-Silicon Validation Engineering Intern in San Jose, California, within the Cadence DDR IP group. This on-site internship role involves validating both system-level and electrical performance of internal silicon test chips, debugging silicon issues in collaboration with analog and digital design teams, and delivering high-quality characterization reports. The intern will work cross-functionally to ensure product functionality, reliability, and successful deployment.

• Validate system-level and electrical performance of internal silicon test chips.
• Debug silicon issues in close collaboration with analog and digital design teams.
• Deliver high-quality characterization reports.
• Collaborate cross-functionally to ensure product functionality, reliability, and successful deployment.
• Drive system and electrical testing efforts to identify silicon issues and contribute to debugging efforts.

• Bachelor’s or master’s degree in electrical engineering with 0–2 years of relevant work experience.
• Very good fundamentals in analog and digital electronics, RTL, signal integrity, and control systems.
• Excellent written and verbal communication skills.
• Ability to work collaboratively in a team environment.
• Prior experience in the hardware semiconductor or electronics industry is a plus.
• Experience with script-based test automation in Python, C, or other scripting tools is a plus.

On-site internship in San Jose, California.

Cadence is an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to race, color, sex, age, national origin, religion, sexual orientation, gender identity, status as a veteran, disability, or any other protected class.