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Post-Silicon Validation Intern: Characterization & Debug

Job in San Jose, Santa Clara County, California, 95199, USA
Listing for: Cadence Design Systems
Apprenticeship/Internship position
Listed on 2026-06-19
Job specializations:
  • Engineering
    Electronics Engineer, Electrical Engineering, Test Engineer, Hardware Engineer
Salary/Wage Range or Industry Benchmark: 10000 - 60000 USD Yearly USD 10000.00 60000.00 YEAR
Job Description & How to Apply Below

Cadence Design Systems in San Jose, California, is seeking a Post-Silicon Validation Engineering Intern to validate and characterize internal silicon test chips. This on-site internship offers the chance to work closely with design teams, delivering high-quality reports and ensuring product functionality.

Ideal candidates should be pursuing a Bachelor’s or Master’s degree in electrical engineering and possess good analytical skills, proficiency in analog and digital electronics, and effective communication abilities.

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