Test Engineer - San Jose, CA Onsite
Listed on 2026-06-19
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Engineering
Test Engineer, Hardware Engineer
Test Engineer
12 Months
San Jose, CA
Description:
JOB DUTIES:
Defining and implementing test plans, developing System Verilog /UVM based unit level test benches, including stimulus, checkers, monitors and assertions, analyzing and debugging regression fails, and developing and analyzing functional coverage on North Bridge / Data Fabric Design.
Key skills are software (System Verilog, C/C++, object oriented programming, scripting (e.g. Perl), x86 assembly), Verilog simulation and modeling, knowledge of computer and peripheral architectures.
EXPERIENCE AND
EDUCATION:
Bachelors and 0-2 years experience, or Masters and 2+ years experience;
Requires demonstrated technical expertise in functional verification of microprocessor designs;
Experience with Verilog, System Verilog, UVM, programming in Perl & C/C++, logic simulation is a requirement;
Requires very strong understanding of computer architecture;
Experience of assertion based design strategies, code coverage, functional coverage etc will be an asset;
Requires good communication and technical leadership skills
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