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SystemVerilog​/UVM Verification Engineer; Front-End

Job in San Jose, Santa Clara County, California, 95199, USA
Listing for: Advanced Micro Devices
Full Time position
Listed on 2026-06-19
Job specializations:
  • Engineering
    Test Engineer, Hardware Engineer, Electronics Engineer
Salary/Wage Range or Industry Benchmark: 95000 - 120000 USD Yearly USD 95000.00 120000.00 YEAR
Job Description & How to Apply Below
Position: SystemVerilog/UVM Verification Engineer (Front-End)

Advanced Micro Devices is seeking a Front-End Verification Engineer in San Jose, CA. You will validate the functionality of next-generation AMD/Xilinx devices by collaborating with cross-functional teams and driving verification execution from definition through silicon readiness.

The ideal candidate has strong skills in digital design and advanced verification techniques including System Verilog and UVM. Responsibilities include defining and owning test plans and verification tasks within a collaborative environment.

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