Senior ASIC Physical Design Technical Lead

The application window is expected to close on: 07/01/2026

The Common Hardware Group (CHG) delivers the silicon, optics, and hardware platforms powering Cisco’s core Switching, Routing, and Wireless products. We design networking hardware for enterprises, service providers, the public sector, and nonprofit organizations worldwide. As part of the team behind Cisco Silicon One—the industry’s only unified silicon architecture spanning top-of-rack switches to web-scale data centers—you’ll help shape Cisco’s groundbreaking solutions by designing, developing, and testing some of the most advanced ASICs in the industry.

• Fullchip Floorplan by understanding the architecture of the design and IP placement constraints
• Collaborate with the system and package design teams to understand the requirements and incorporate into the fullchip floorplan
• Perform hierarchical implementation flow, including partition, pin assignment, clock plan and bump planning
• RTL-to-GDSII implementation:
  Floorplan, Power Grid plan, place and route, static timing analysis, power integrity, physical verification and equivalence checks with a focus on performance, power and die size optimization.
• Analyze existing tool flows and methodologies, identifying efficiency gaps and implementing incremental or transformative enhancements.
• Work closely with RTL, DFT, implementation, EDA vendors, and tool/flow teams to enable best-in-class design methodology.
• Proficiency in low‑power design methodologies using UPF
• Work with Foundry and standard cell IP vendors to define the signoff methodologies and validate/adjust them when you receive feedback from Post‑Silicon Validation teams
• Good team player and curiosity to use the AI tools for productivity improvements

• Bachelor’s Degree in Electrical Engineering with 12+ years of Physical Design experience or Master’s Degree in Electrical Engineering with 8+ years of Physical Design experience, or PhD in Electrical Engineering with 5+ years of Physical Design experience.
• Experience working on Fullchip activities.
• Experience with RTL2
  
  GDSII flow and design tapeouts in 7‑nm/5‑nm/3‑nm or below process technologies.
• Experience working with EDA tools like Innovus, Tempus/Primetime, Redhawk/Voltus or Calibre/Pegasus.

• Experience with hierarchical design, timing closure, physical convergence, and power integrity analysis.
• Experience with static timing analysis and concepts, defining timing constraints and exceptions, corners/voltage definitions.
• Experience in Fullchip floor‑planning and power grid planning.
• Experience with custom clock (H‑Tree or Mesh) at chip level.
• Experience with Python and usage of AI tools by giving accurate prompts
• Leadership/mentorship experience.