Senior Principal Physical Design Engineer; -Level Floorplanning & STA
Job in
San Jose, Santa Clara County, California, 95199, USA
Listed on 2026-06-20
Listing for:
ACL Digital
Full Time
position Listed on 2026-06-20
Job specializations:
-
Engineering
Engineering Design & Technologists, Systems Engineer, Hardware Engineer
Job Description & How to Apply Below
We are looking for a Senior Principal Physical Design Engineer to own the top-level floorplan, global power networks, and timing budgets for our next-generation architecture.
Requirement- Advanced Chip Ownership: Proven track record of owning full-chip top-level integration, floor planning, and hierarchical design
- Dual-Tool Fluency: Expert-level mastery of both Cadence Innovus and Synopsys Fusion Compiler
- Sign-off Expertise: Strong background in top-level SDC authoring, timing budgets, and EM/IR sign-off workflows
- Ecosystem Management: Exceptional collaboration skills to bridge technical gaps between internal block owners and external ASIC/IP vendors
Position Requirements
10+ Years
work experience
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