Senior Physical Design Engineer: Chip PV & Tapeout
Job in
San Jose, Santa Clara County, California, 95199, USA
Listed on 2026-06-20
Listing for:
Celero Communications, Inc.
Full Time
position Listed on 2026-06-20
Job specializations:
-
Engineering
Electrical Engineering, Systems Engineer, Electronics Engineer, Test Engineer
Job Description & How to Apply Below
Celero Communications, Inc. in San Jose, CA is seeking a Physical Design Engineer to lead complex digital block and full-chip implementations. The role involves execution of Physical Verification on advanced TSMC nodes and collaboration with analog design teams.
Applicants should have a Bachelor’s or Master’s in Electrical Engineering and over 5 years of chip verification experience. The position offers a competitive salary range from $150,000 to $250,000 annually based on skills and experience.
#J-18808-LjbffrPosition Requirements
10+ Years
work experience
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