Level PD Architect: Chip Floorplan & Power
Job in
San Jose, Santa Clara County, California, 95199, USA
Listed on 2026-06-20
Listing for:
ACL Digital
Full Time
position Listed on 2026-06-20
Job specializations:
-
Engineering
Engineering Design & Technologists, Systems Engineer
Job Description & How to Apply Below
ACL Digital is seeking a Senior Principal Physical Design Engineer to take ownership of the top-level floorplan and global power networks for its next-generation architecture.
The ideal candidate will have proven expertise in full-chip integration, mastery of Cadence Innovus and Synopsys Fusion Compiler, and the ability to manage timing budgets and EM/IR sign-off workflows. Exceptional collaboration skills are essential to work closely with both internal and external teams.
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