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Senior DFT Engineer; IC – Scan/ATPG, JTAG, ‑Site SJ
Job in
San Jose, Santa Clara County, California, 95199, USA
Listed on 2026-06-20
Listing for:
Dormont Manufacturing Co
Full Time
position Listed on 2026-06-20
Job specializations:
-
Engineering
Quality Engineering, Test Engineer
Job Description & How to Apply Below
Dormont Manufacturing Co is seeking a Design For Test Engineer III to work on advanced DFT implementations for Networking chips. Candidates should have 5–7 years of experience with expertise in scan-insertion, ATPG, and verification tools.
This full-time role based in San Jose, CA offers a competitive salary ranging from $95,900 to $170,500 annually and benefits like medical insurance, 401(k) matching, and tuition reimbursement.
#J-18808-LjbffrPosition Requirements
10+ Years
work experience
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