Micro-architect​/Logic Designer, Coherent Interconnect

Position Summary:

Samsung, a world leader in advanced semiconductor technology, is founded on a simple philosophy – the endless pursuit of excellence will create a better world for all. At Samsung Austin Research and Development Center (SARC) and Advanced Computing Lab (ACL), we are building a center of excellence for Intellectual Property (IP) that is applied to high‑performance computing devices consumed by millions of people around the world.

• Lead the micro‑architecture development of custom coherent interconnect IP and last level cache (LLC) blocks.
• Partner with system architects, verification, performance/power, and design implementation teams.
• Own and drive critical coherent interconnect RTL design, performance and power optimization, logic debug, and timing closure.
• Produce high‑quality RTL on schedule while meeting PPA goals.
• Collaborate with verification to verify functionality and correctness.
• Work with implementation to achieve timing and area targets.
• Engage with performance and power teams to achieve performance and power objectives.
• Resolve implementation‑level details with physical design and CAD teams.
• Mentor junior engineers in the team.

• 10+ years of experience with a Bachelor’s degree in Computer Science/Engineering, or 8+ years with a Master’s, or 6+ years with a PhD.
• Strong background owning and driving RTL design of coherent interconnect, memory controller, or LLC sub‑blocks for high‑performance digital designs.
• Demonstrated architectural through‑RTL design experience on high‑performance digital designs.
• Verilog expertise and deep understanding of ASIC design flow including RTL design, verification, logic synthesis, prototyping, DFT, timing analysis, floor‑planning, ECO, bring‑up, and lab debug.
• Knowledge of system caches, directory snoop filter protocols, and on‑chip network topologies (mesh, ring, crossbar).
• Familiarity with ARM AMBA5 CHI, AMBA4 ACE, or AXI coherent interconnect and bus protocols.
• Experience leading and mentoring a team of engineers.
• Strong communication and interpersonal skills; ability to work in a dynamic, global team.
• Preferred:
  Verilog/VHDL, scripting (Perl, Python), STA, DFT, ECO flows; proficiencies in AMBA, ACE, AXI, CHI protocols; knowledge of coherent interconnect, memory controller, cache design.

Base pay range: $151,000 – $251,800, subject to education, skills, qualifications, and location.

• Medical, dental, vision, and life insurance.
• 401(k) plan.
• Free onsite lunch and employee purchase program.
• Tuition assistance (after 6 months).
• Paid time off and student loan program.
• Wellness incentives and many additional benefits.
• Eligibility for MBO bonus compensation and long‑term incentive plan.
• Relocation assistance may be considered.

U.S. Export Control:
The position requires the ability to access information subject to U.S. export control restrictions. Applicants must be eligible to receive the required government authorization.

Trade Secrets:
By submitting an application, the applicant agrees not to disclose or induce disclosure of any confidential or proprietary information belonging to current or former employers.

* Samsung Electronics America, Inc. and its subsidiaries are committed to employing a diverse workforce and provide Equal Employment Opportunity for all individuals regardless of race, color, religion, gender, age, national origin, marital status, sexual orientation, gender identity, status as a protected veteran, genetic information, status as a qualified individual with a disability, or any other characteristic protected by law.