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Digital Implementation and Signoff, Principal AE

Job in San Jose, Santa Clara County, California, 95199, USA
Listing for: Cadence
Full Time position
Listed on 2026-06-21
Job specializations:
  • Engineering
    Systems Engineer
Salary/Wage Range or Industry Benchmark: 123200 - 228800 USD Yearly USD 123200.00 228800.00 YEAR
Job Description & How to Apply Below

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

As an expert Digital Implementation and Signoff Field Applications Engineering (AE), you will work side‑by‑side with our leading edge customers. With your expertise, you’ll help them deploy Cadence’s market‑leading technologies in Synthesis, P&R, and Signoff to meet/exceed their PPA targets, achieve faster design closure, and turn their design concepts into reality. The greater your powers, the more business opportunities you’ll help bring to the table.

You will also work directly with the Cadence R&D group to drive the customer requirements and influence the direction of Cadence next‑generation products and technologies.

Key Responsibilities
  • Be part of a team of Application Engineers providing technical support to Cadence customers in the areas of Backend Digital Design Implementation and Signoff, including Place and Route, Design Closure, and timing/power signoff.
  • Guide customers on how to best utilize Cadence technologies to achieve their design goals and meet project schedules.
  • Collaborate with team to conduct technical presentations and product demonstrations.
  • Drive technical evaluations/benchmarks to success.
  • Work closely with R&D to enhance the tools and methodologies to meet and exceed customer’s requirements.
  • Drive adoption and proliferation of Cadence tools and technologies.
  • Provide guidance to the team to amend and augment the flow as needed using Tcl and/or other programming skills to meet objectives and improve results/flows.
Job Requirements
  • 12+ years of industry Physical Design experience.
  • BS degree in Computer Science, Engineering, Electrical, or related field.
  • Strong knowledge in Digital Design Fundamentals, Semiconductor fundamentals, and Static Timing Analysis.
  • Prior experience with IC digital implementation flows and back‑end EDA tools including Place and Route, IR Drop, back‑end design timing and power closure.
  • Experience with advanced nodes 10nm and below.
  • Experience in scripting languages such as Tcl, Perl, Python.
  • Strong customer‑facing communication and problem‑solving skills.
  • Strong personal drive for continuous learning and expanding professional skill sets.
  • Strong verbal, written, and customer communication skills.
  • MS degree in Computer Science, Engineering, Electrical, or related field.
  • Prior experience with IC digital implementation flows and front‑end EDA tools including Synthesis, DFT, and Logical Equivalence Checking.
  • Prior experience with Cadence tools such as Genus, Innovus, Conformal, Tempus, Modus, Voltus or ICC, ICC2, DC or Primetime.
  • Experience with advanced nodes 5nm and below.
  • Capture best practices and lessons learned from current evaluations/benchmarks and utilize to improve efficiency and success rate in next engagements.

The annual salary range for California is $123,200 to $228,800. You may also be eligible to receive incentive compensation: bonus, equity, and benefits. Sales positions generally offer a competitive On Target Earnings incentive compensation structure. Our benefits programs include: paid vacation and paid holidays, 401(k) plan with employer match, employee stock purchase plan, and a variety of medical, dental, and vision plan options.

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